The present invention relates generally to integrated circuit (IC) designs, and more particularly to testing of one-time-programmable (OTP) memories.
After a memory IC is manufactured, all of its memory cells as well as the associated logic circuits must be tested before being shipped to a customer. Because the memory cells occupy relatively larger chip area than the logic circuits, and therefore have bigger chance of having defects, conventional memory testing has been focused on testing the memory cells through repeatedly writing to and reading from the memories cells. Testing the memory cells will inevitably test the associated logic circuits as the logic circuits perform the address decoding, reading and writing functions. Random access memories, such as dynamic random access memory (DRAM) and static random access memory (SRAM), as well as nonvolatile Flash memory can be tested by the above conventional testing method, because cells in these memories can be repeatedly written to and read from.
However, the conventional testing method cannot quickly test only the logic circuits, as accessing all the cells in a modern high-density memory takes long time. More over, some memories, such as OTP memory, do not allow for repeated write operation. Therefore, logic circuit in such memories cannot be tested through testing the memory cells. In case of the OTP memory, the memory cells can only be written once, and such right is reserved for an end user.
As such, what is desired is a system and method for quickly testing the logic circuits in a memory IC without affecting the usability thereof.